1. Field of the Invention
The present invention relates to improvements in power devices. The present invention is specifically directed to packaging for high temperature applications.
2. Description of the Known Art
As will be appreciated by those skilled in the art, wide band gap materials, such as Silicon Carbide, SiC, and Gallium Nitride, GaN, are ideal for next generation power devices, offering superior performance in comparison to traditional Silicon, Si, based switches. In particular, substantially higher voltage breakdown strengths allow devices to be fabricated with blocking layers up to an order of magnitude thinner, directly reducing channel resistances and increasing switching speed. Wide band gap power devices are a maturing technology with a growing selection of power components, diodes, MOSFETs, JFETs, HEMTs, and BJTs, available on the commercial market from a diversity of vendors.
While the intrinsic features of these materials, combined with advanced device design and fabrication techniques, have created power switches with unprecedented levels of performance, their true potential is hindered by conventional power packages, materials, attaches, and layout techniques.
In order to unlock the revolutionary performances promised by wide band gap power devices, the power packaging, gate drive, busing, heat removal, and control systems must be specifically designed around high temperature wide band gap technology. With these tools, a system level designer may significantly increase the efficiency and reduce the weight and volume of the entire power conversion system including motor drives, inverters, battery chargers, etc. This includes a reduction of the power module itself, reduced size or complexity of the heat removal system such as a heat sink, cold plate, etc., decreased output filter size by utilizing high frequency switching, and placement in high ambient environments such as under the hood of a vehicle without the need for thermal isolation.
High Performance Discrete Packaging
At the module level, multiple devices are co-packaged in various topologies such as half-bridge, full-bridge and paralleled in order to reach the current level desired or until the available area in the module is occupied. While this is a powerful approach for very high current levels like those >100 A and for large, integrated systems, there are few options at the discrete level, only single switches and a diode, if necessary for currents in the 50-100 A range that also offer low inductance, high temperature capability, and flexibility of use. Standard discrete or small footprint wire bonded power packages include transistor outline 10, TO packages, such as the TO-254, and small outline transistor 20, SOT, Isotop packages, each displayed in FIG. 1. While these packages are effective for conventional silicon, Si, devices, limitations are clearly encountered with the high frequency, high current density performances characteristic of wide band gap devices.
TO style packages 10 are often current limited due to small cross sectional area of the pin contacts, have a thin base plate which is not effective for heat spreading, and only have one mounting point at the edge of the package, making it difficult to form an efficient thermal path between the package and the heat removal system. Isotop packages 20 are capable of higher currents due to their blade style connections and have improved mounting features; however, they can suffer from a high lead inductance and are generally constructed with materials not capable of reaching temperatures above 175° C.
As shown in FIG. 2, vertical power devices 30 predominately have upper pads metallized with aluminum and are intended for wire bonding. Current flows through the die area vertically, which is ideal for minimizing the on-resistances. A metallized backside connection is soldered to a thermally and electrically conductive substrate, forming an efficient path, utilizing the entire die footprint, for the heat generated in the device during conduction and switching to be transferred to a heat sink. FIG. 2 displays a variety of wire bonded wide bandgap power devices.
Wire bonds are a core element providing topside interconnection in the majority of power modules today. However, they are a substantial source of parasitic impedances and reliability issues especially at higher temperatures. Parasitic inductances contributed by the packaging and internal interconnection of a power electronic module are a major factor limiting switching speed and performance in a power conversion system. This is even more relevant for high performance wide band gap power switches, which feature rise and fall times in the 10 s of ns. Wire bond interconnects impose enormous challenges for electronic package designers, including:                Considerable parasitic impedances due to small wire cross-sections such as 0.005 in to 0.020 in, relatively long lengths, and the need for bond loops.        Current crowding on die pads.        Under-utilization of the entire bonding surface.        Possibility of fusing during a current spike.        Stability in high vibration environments.        Clearance issues for the wire bonding equipment.        Potential reliability issues during power cycling.        Metallurgical compatibility concerns.        
FIG. 3 shows an example of a lateral power device 40. In low power systems, such as high frequency RF devices, and semiconductor technologies where only lateral devices may be formed, including GaN, there are multiple wire bondless options in production. Many high frequency devices utilize a flip-chip attach, in which an array of electrical connections are established to the device by forming pillars of either copper, solder alloys, or gold balls on the device. These pillars are then soldered or ultrasonically welded to the package or another device. This approach, however, is a critical issue for power, as the pillar arrays form a poor thermal connection with the rest of the system due to their restrictive geometry. The thermal connection is further impeded by the use of underfill that is a stress relieving and voltage blocking material applied between and around the bumps, which generally has a low thermal conductivity. The backside of the device is typically left as the bare substrate i.e., Si, SiC, sapphire, etc. and is attached with epoxy, which also has a comparatively poor thermal conductivity to a soldered attach.
Accordingly, for both lateral and vertical devices, hereafter inclusively referred to as generic die device 60 a dual sided solder connection is desirable, providing an ideal electrical and thermal connection to both sides. This style of attach takes advantage of the efficient heat removal nature of a vertical device with the wire bondless interconnection of a flip chip attach. These metallic connections would be low profile, low inductance, low resistance, and highly effective at transferring heat. A dual sided connection requires vertical devices to have solderable top side metallizations and lateral devices to have electrical vias through the die and a solderable backside metallization. Lateral devices without backside connections could be incorporated with a thermally conductive epoxy, which an associated tradeoff in current density.
Power modules or packages are known in various forms. Patents include U.S. Pat. No. 7,687,903, issued to Son, et al. on Mar. 30, 2010 entitled Power module and method of fabricating the same; U.S. Pat. No. 7,786,486 issued to Casey, et al. on Aug. 31, 2010 entitled Double-sided package for power module; U.S. Pat. No. 8,018,056 issued to Hauenstein on Sep. 13, 2011 entitled Package for high power density devices; U.S. Pat. No. 8,368,210 issued to Hauenstein on Feb. 5, 2013 entitled Wafer scale package for high power devices; U.S. Pat. No. 6,307,755 issued to Williams, et al. on Oct. 23, 2001 entitled Surface mount semiconductor package, die-leadframe combination and leadframe therefore and method of mounting leadframes to surfaces of semiconductor die. Each of these patents is hereby expressly incorporated by reference in their entirety.